1. Field of the Invention
This invention relates to a bus linkage unit for connecting a bus of a computer system with a bus of an expansion box or a bus of another computer system through a signal transfer path in which the signal mode is different from that of said buses, and more particularly, a bus linkage unit for enabling wired-OR signal lines to be connected without interlocking.
2. Prior Art
When the functions of a conventional personal computer are expanded, it is conventional to lead out all signal lines of the bus through a connector or the like to connect to a bus within an expansion box. However, as the performance of personal computers is more and more sophisticated year after year, high speed signals increase in these over the bus, and the number of signal lines significantly increases for the bus, resulting in the following problems:
(1) The waveforms of signals are distorted as the signal lines, through which high-speed signals are carried, are extended. PA1 (2) High-speed signals give causes a problem of unnecessary emission. PA1 (3) External noise tends to easily intrude, causing malfunctions. PA1 (4) The increased number of signal lines necessitates using multicontact connectors. PA1 (5) Use of multicontact connectors tends to lower reliability. PA1 (1) In one system, one device drives signal lines to low voltage level, this level is transferred to the other system through a communication path, and the signal lines in that system are driven to low voltage level. Then, the low voltage level of the signal lines of said other system is transferred to said one system, and the signal lines of said system are driven to low voltage level. Even if said device stops the low voltage drive in said one system, signal lines are continued to be driven to low voltage level sent from the communication path. PA1 (2) The above problem can be prevented through the communication path if the communication path itself is driving to low voltage level. However, if separate devices drive the same signal to low voltage at the same time on both sides of the communication path, there arises such a situation as that the communication path continuing to drive both sides to low voltage level occurs.
These problems used to put severe restrictions on the extendibility of sophisticated personal computers. To code with these problems, it is proposed to link a bus of a computer to a bus of another computer or a bus of peripheral equipment through a communication link.
For instance, the computer system disclosed in Published Unexamined Patent Application (PUPA) No. 59071527 is to link a host processor and remote equipment with one communication link, and to support cycle stealing transfer.
Also, the system bus data linkage unit disclosed in PUPA No. 3-4351, is to provide special linkage modules for the respective parallel buses in order to connect, for example, two parallel buses with a serial link. Thus, when data is sent from the system initiator of one parallel bus to the system target of the other parallel bus, the link module of the one parallel bus simulates the other parallel data, and converts the parallel data into serial data, which is then sent to the other parallel bus. The link module of the other parallel bus converts the serial data into parallel data, simulates the system initiator, and transfers the parallel data to the system target. In such a configuration as mentioned above where two systems are connected through a communication path, attention must be paid to the handling of wired-OR signal lines. That is, in a bus of a personal computer or the like, negative logic OR is taken on signal lines in some cases by driving the same signal line with an open collector or open-drain type drive element so that an unspecified number of devices can transfer a specific request. An example of such a signal line is the interrupt request signal line in the bus architecture in the specifications for MicroChannel (a trademark of International Business Machines Corporation). If such signal lines are connected through a transfer path in which a signal mode is different from that of the bus, such as an optical fiber communication path for example, so that signal levels are simply transferred with each other and participated in wired-OR by an open collector at the destination of each communication path, a stiff situation such as the following is generated (interlock).
The following are prior art references relevant to this invention:
IBM Technical Disclosure Bulletin, Vol. 28, No. 6, pp. 2346-2347, "STACKABLE UNIT PACKAGING CONCEPT," (Nov. 1985): This publication discloses a technique for connecting signal lines between two functional units through a connector by putting one functional unit on the housing of the other functional unit equipped with extendable buses.
IBM Technical Disclosure Bulletin, Vol. 26, No. 10A, pp. 5147 -5152, "EXTENDED DATA BUS WITH DIRECTION AND ENABLE CONTROL FEATURES," (March 1984): This publication discloses a method of controlling data transfer directions such that a computer system and an expansion system are linked in parallel and directions of data transfer are controlled by detecting from which of the two systems the DMA request in question has been issued.
PUPA No. 56-166536: This gazette discloses a technique for asynchronous communication between interface buses such that a pair of extenders are installed between two interface buses, and asynchronous communication control is exercised between the extenders to establish asynchronous communication between the interface buses. It also discloses a technique for connecting two buses in parallel through the use of an optical cable.
IBM Technical Disclosure Bulletin, Vol. 19, No. 8, pp. 3139-3143, "SERIAL CHANNEL TO I/O INTERFACE," (Jan. 1977): This publication discloses a serial I/O interface replacing a parallel I/O interface. This interface allows data to be transferred serially by use of frames or packets each consisting of a flag and its subsequent serial data.
PUPA No. 3-88055, 1991: This gazette discloses a technique for setting up a data chain (CCW record) flag and a command chain (CCW record link) flag in an extender connecting a serial channel to a device on a parallel bus.
Patent application Ser. No. 3-15926: This patent application describes an invention relating to speeding up serial data transfer between a channel and a device by use of a microcode routine.
PUPA No. 62-251951: This patent application discloses the invention whereby a transfer byte count can be included in the command field of an extender connecting a serial channel with a parallel device.
PUPA No. 2-230356, 1990: This patent application describes a technique for holding levels in registers and looking in via main system when an interrupt signal is notified to the main system from an expansion system.
PUPA No. 1-93941, 1989: This patent application describes a technique for serially transferring a snap shot of parallel signals and holding said transferred signals in shift registers.
However, none of the above references mentions about the interlock of wired-OR signal lines that is generated when the buses of two different systems are connected by a transfer path in which the signal mode is different from those of the buses.